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Author Topic: a pfSense roadmap  (Read 842 times)

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Offline jits

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Re: a pfSense roadmap
« Reply #15 on: February 27, 2015, 06:13:02 am »
Wow!

There is just something magical reading the project map for 3.0 while feasting on a Cadbury's almonds and raisin chocolate bar.

But...any consideration for the Wireless ISP guys? No MPLS implementation? No MIPS hardware as yet? Can these be options for consideration for small ISP types?

Offline Michael Sh.

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Re: a pfSense roadmap
« Reply #16 on: February 27, 2015, 05:28:03 pm »
Fortran IV - holes in punched cards can be seen. And the 6 position is marked usual.  ;)
Python? Programming with spaces? Loss/extra space and the program behaves unpredictably? Forget copy/paste, move pieces of code, and so on?
Great...  :(

Offline gonzopancho

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Re: a pfSense roadmap
« Reply #17 on: February 27, 2015, 11:37:30 pm »
Wow!

There is just something magical reading the project map for 3.0 while feasting on a Cadbury's almonds and raisin chocolate bar.

But...any consideration for the Wireless ISP guys? No MPLS implementation? No MIPS hardware as yet? Can these be options for consideration for small ISP types?

Did I say there would not be MPLS, or GRE support?

No, I did not.   It's a path, jtls.

In any case, 2.x is always an option on existing hardware.

Offline jimp

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Re: a pfSense roadmap
« Reply #18 on: March 02, 2015, 12:34:07 pm »
Fortran IV - holes in punched cards can be seen. And the 6 position is marked usual.  ;)
Python? Programming with spaces? Loss/extra space and the program behaves unpredictably? Forget copy/paste, move pieces of code, and so on?
Great...  :(

If it forces us to maintain proper style and spacing, it's not a bad thing.
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Offline gonzopancho

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Re: a pfSense roadmap
« Reply #19 on: March 02, 2015, 01:11:36 pm »
Fortran IV - holes in punched cards can be seen. And the 6 position is marked usual.  ;)
Python? Programming with spaces? Loss/extra space and the program behaves unpredictably? Forget copy/paste, move pieces of code, and so on?
Great...  :(

If it forces us to maintain proper style and spacing, it's not a bad thing.

python is a lot like lisp without the parenthesis.   Once you figure that out, it gets easy.

Offline router_wang

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Re: a pfSense roadmap
« Reply #20 on: March 02, 2015, 01:40:12 pm »

The next PC Engines board has a Jaguar (so: AES-NI) 2 or 4 core CPU, 2 or 4GB RAM (ECC on the 4GB model) and (wait for it), Intel NICs (I imagine these will be i217/218 class.)


Intel NIC's? That is awesome, where did you see this?

Offline jimp

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Re: a pfSense roadmap
« Reply #21 on: March 02, 2015, 02:13:15 pm »
[...]and the program behaves unpredictably?[...]

Forgot something:

Unpredictable behavior will most likely be caught by the copious amount of unit tests we'll surely be adding during the rewrite.
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Offline gonzopancho

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Re: a pfSense roadmap
« Reply #22 on: March 02, 2015, 06:37:57 pm »

The next PC Engines board has a Jaguar (so: AES-NI) 2 or 4 core CPU, 2 or 4GB RAM (ECC on the 4GB model) and (wait for it), Intel NICs (I imagine these will be i217/218 class.)


Intel NIC's? That is awesome, where did you see this?

Pascal told Chrs months ago.

Offline kejianshi

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Re: a pfSense roadmap
« Reply #23 on: Yesterday at 12:12:29 am »
Sounds like nice hardware.  These will work well when its 32C outside, hotter inside and no airconditioning?  (Its a serious question)

Offline gonzopancho

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Re: a pfSense roadmap
« Reply #24 on: Yesterday at 02:29:23 am »
I don't design the PC Engines boards. 

The RCC-VE & RCC-DF will.

Offline dennypage

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Re: a pfSense roadmap
« Reply #25 on: Yesterday at 04:45:26 pm »
Totally

apinger needs a re-write.  It's garbage code.

Offline grandrivers

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Re: a pfSense roadmap
« Reply #26 on: Yesterday at 07:28:31 pm »
rewrite can't happen soon enough dual wan failover is what brought me to Pfsense on my connections it no longer works